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PRELIMINARY
CY14E104K/CY14E104M
4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock
Features

Watchdog timer Clock alarm with programmable interrupts Capacitor or battery backup for RTC Commercial and industrial temperatures 44/54-pin TSOP II package Pb-free and RoHS compliance
15 ns, 20 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14E104K) or 256K x 16 (CY14E104M) Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap(R) nonvolatile elements is initiated by software, device pin, or AutoStore(R) on power down RECALL to SRAM initiated by software or power up High reliability Infinite read, write, and recall cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 5V +10% operation Data integrity of Cypress nvSRAM combined with full featured Real-Time-Clock
Functional Description
The Cypress CY14E104K/CY14E104M combines a 4 Mbit nonvolatile static RAM with a full featured real-time-clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM is read and written an infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The real-time-clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for one time alarms or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control.
Logic Block Diagram
VCC VCAP VRTCcap VRTCbat
Address A0 - A18[1]
CE OE WE
[1]
DQ0 - DQ7 HSB INT X1 X2
CY14E104K CY14E104M
BHE BLE
VSS
Note 1. Address A0 - A18 and DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation Document #: 001-09604 Rev. *H
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 20, 2008
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PRELIMINARY
CY14E104K/CY14E104M
Pinouts
Figure 1. Pin Diagram - TSOP II
INT [3] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [2] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 VRTCcap VRTCbat
INT NC A0
[3]
44 - TSOP II
(x8)
Top View (not to scale)
A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
54 - TSOP II
(x16)
Top View (not to scale)
HSB NC [2] A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC
X1 X2
VRTCcap VRTCbat
Pin Definitions
Pin Name A0 - A18 A0 - A17 IO Type Input Description Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
DQ0 - DQ7 Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation.
DQ0 - DQ15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on operation. No Connect No Connects. This pin is not connected to the die. Input Input Input Input Input Output Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Byte High Enable, Active LOW. Controls DQ15 - DQ8. Byte Low Enable, Active LOW. Controls DQ7 - DQ0. Crystal Connection. Drives crystal on start up. Crystal Connection. For 32.768 kHz crystal.
NC WE CE OE BHE BLE X1 X2 VRTCcap VRTCbat
Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used. Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.
Notes 2. Address expansion for 8 Mbit. NC pin not connected to die. 3. Address expansion for 16 Mbit. NC pin not connected to die.
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PRELIMINARY
CY14E104K/CY14E104M
Pin Definitions (continued)
Pin Name INT VSS VCC HSB VCAP IO Type Output Ground Description Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain). Ground for the Device. Must be connected to ground of the system.
Power Supply Power Supply Inputs to the Device. 5.0V +10%, -10% Input/Output Hardware Store Busy. When LOW this output indicates that a hardware store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected. (connection optional) Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements.
Device Operation
The CY14E104K/CY14E104M nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14E104K/CY14E104M supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.
AutoStore Operation
The CY14E104K/CY14E104M stores data to the nvSRAM using one of three storage operations. These three operations are: Hardware Store, activated by HSB; Software Store, activated by an address sequence; AutoStore, on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14E104K/CY14E104M. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 2. AutoStore Mode
Vcc
SRAM Read
The CY14E104K/CY14E104M performs a read cycle when CE and OE are LOW and WE and HSB are HIGH. The address specified on pins A0-18 or A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each are accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle #1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle #2). The data output repeatedly responds to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
0.1uF 10kOhm Vcc
WE
V CAP
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the write cycle and must remain stable until CE or WE goes HIGH at the end of the cycle. The data on the common IO pins IO0-7 are written into the memory if it is valid tSD before the end of a WE controlled write or before the end of an CE controlled write. It is recommended that OE be kept HIGH during the entire write cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
V SS
V CAP
Figure 2 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to DC Electrical Characteristics on page 14 for the size of the VCAP. To reduce unnecessary nonvolatile stores, AutoStore and hardware store operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a write operation has taken place. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress. Page 3 of 28
Document #: 001-09604 Rev. *H
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PRELIMINARY
CY14E104K/CY14E104M
Hardware STORE (HSB) Operation
The CY14E104K/CY14E104M provides the HSB pin to control and acknowledge the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14E104K/CY14E104M conditionally initiates a STORE operation after tDELAY. An actual STORE cycle begins only if a write to the SRAM has taken place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. SRAM read and write operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14E104K/CY14E104M continues SRAM operations for tDELAY. During tDELAY, multiple SRAM read operations may take place. If a write is in progress when HSB is pulled LOW it is allowed a time, tDELAY, to complete. However, any SRAM write cycles requested after HSB goes LOW is inhibited until HSB returns HIGH. During any STORE operation, regardless of how it is initiated, the CY14E104K/CY14E104M continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY14E104K/CY14E104M remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
Because a sequence of reads from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following read sequence must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8FC0 Initiate STORE cycle The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for read and write operations.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4C63 Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM is again ready for read and write operations. The RECALL operation in no way alters the data in the nonvolatile elements.
Hardware RECALL (Power Up)
During power up, or after any low power condition (VCC < VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The CY14E104K/CY14E104M software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.
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PRELIMINARY
CY14E104K/CY14E104M
Table 1. Mode Selection CE H L L L WE X H L H OE X L X L A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active Active Active[4, 5, 6]
L
H
L
Active[4, 5, 6]
L
H
L
Active ICC2[4, 5, 6]
L
H
L
Active[4,5,6]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable
The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable If the AutoStore function is disabled or re-enabled, a manual STORE operation (hardware or software) is issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Notes 4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 5. While there are 19 address lines on the CY14E104K/CY14E104M, only the lower 16 lines are used to control software modes. 6. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
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PRELIMINARY
CY14E104K/CY14E104M
Data Protection
The CY14E104K/CY14E104M protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14E104K/ CY14E104M is in a write mode (both CE and WE LOW) at power up, after a RECALL, or after a STORE, the write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Backup Power
The RTC in the CY14E104K/CY14E104M is intended for permanently powered operations. The VRTCcap or VRTCbat pin is connected depending on whether a capacitor or battery is chosen for the application. When the primary power, VCC, fails and drops below VSWITCH, the device switches to the backup power supply. The clock oscillator uses very little current, which maximizes the backup time available from the backup source. Regardless of clock operation with the primary source removed, the data stored in nvSRAM is secure, having been stored in the nonvolatile elements when power was lost. During backup operation, the CY14E104K/CY14E104M consumes a maximum of 300 nanoamps at 2 volts. Capacitor or battery values must be chosen according to the application. Backup time values based on maximum current specifications are shown in the following table. Nominal times are approximately three times longer. Table 2. RTC Backup Time Capacitor Value 0.1F 0.47F 1.0F Backup Time 72 hours 14 days 30 days
Noise Considerations
Refer CY application note AN1064.
Real-Time-Clock Operation
nvTIME Operation
The CY14E104K/CY14E104M offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. Internal double buffering of the clock and the clock or timer information registers prevents accessing transitional internal clock data during a read or write operation. Double buffering also circumvents disrupting normal timing counts or the clock accuracy of the internal clock when accessing clock data. Clock and alarm registers store data in BCD format.
Clock Operations
The clock registers maintain time up to 9,999 years in one second increments. The time can be set to any calendar time and the clock automatically keeps track of days of the week and month, leap years, and century transitions. There are eight registers dedicated to the clock functions, which are used to set time with a write cycle and to read time during a read cycle. These registers contain the time of day in BCD format. Bits defined as `0' are currently not used and are reserved for future use by Cypress. Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3V lithium is recommended and the CY14E104K/CY14E104M sources current only from the battery when the primary power is removed. The battery is not, however, recharged at any time by the CY14E104K/CY14E104M. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFF8 controls the start and stop of the oscillator. This bit is nonvolatile and shipped to customers in the "enabled" (set to 0) state. To preserve the battery life when the system is in storage OSCEN must be set to `1'. This turns off the oscillator circuit extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately 5 seconds (10 seconds maximum) for the oscillator to start. The CY14E104K/CY14E104M has the ability to detect oscillator failure. This is recorded in the OSCF (Oscillator Failed bit) of the flags register at the address 0x1FFF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for "enabled" status. If the OSCEN bit is enabled and the oscillator is not active, the OSCF bit is set. Check for this condition and then write `0' to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the "Base Time" (see Setting the Clock on page 6), which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the `oscillator failed' condition.
Reading the Clock
While the double buffered RTC register structure reduces the chance of reading incorrect data from the clock, stop internal updates to the CY14E104K/CY14E104M clock registers before reading clock data, to prevent reading of data in transition. Stopping the internal register updates does not affect clock accuracy. The updating process is stopped by writing a `1' to the read bit `R' (in the flags register at 0x1FFF0), and does not restart until a `0' is written to the read bit. The RTC registers are then read while the internal clock continues to run. Within 20 ms after a `0' is written to the read bit, all CY14E104K/CY14E104M registers are simultaneously updated.
Setting the Clock
Setting the write bit `W' (in the flags register at 0x1FFF0) to a `1' stops updates to the CY14E104K/CY14E104M registers. The correct day, date, and time is then written into the registers in 24 hour BCD format. The time written is referred to as the "Base Time". This value is stored in nonvolatile registers and used in the calculation of the current time. Resetting the write bit to `0' transfers those values to the actual clock counters, after which the clock resumes normal operation.
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PRELIMINARY
CY14E104K/CY14E104M
If the voltage on the backup supply (either VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail, leading to the oscillator failed condition which is detected when system power is restored. The value of OSCF must be reset to `0' when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on.
Calibrating the Clock
The RTC is driven by a quartz controlled oscillator with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal, usually specified to 35 ppm limits at 25C. This error could equate to +1.53 minutes per month. The CY14E104K/CY14E104M employs a calibration circuit that improves the accuracy to +1/-2 ppm at 25C. The calibration circuit adds or subtracts counts from the oscillator divider circuit. The number of times pulses are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends on the value loaded into the five calibration bits found in the calibration register at 0x1FFF8. Adding counts speeds the clock up; subtracting counts slows the clock down. The calibration bits occupy the five lower order bits in the control register 8. These bits are set to represent any value between 0 and 31 in binary form. Bit D5 is a sign bit, where `1' indicates positive calibration and `0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary `1' is loaded into the register, only the first 2 minutes of the 64 minute cycle are modified; if a binary `6' is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles. That is 4.068 or -2.034 ppm of adjustment for every calibration step in the calibration register. To determine how to set the calibration, the CAL bit in the flags register at 0x1FFF0 is set to `1', which causes the INT pin to toggle at a nominal 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.010124 Hz indicates a +20 ppm error, which requires the loading of a -10 (001010) into the calibration register. Note that setting or changing the calibration register does not affect the frequency test output frequency.
Depending on the match bits, the alarm can occur as specifically as one particular second on one day of the month, or as frequently as once per second continuously. The MSB of each alarm register is a match bit. Selecting none of the match bits (all 1s) indicates that no match is required. The alarm occurs every second. Setting the match select bit for seconds to `0' causes the logic to match the seconds alarm value to the current time of day. Since a match occurs for only one value per minute, the alarm occurs once per minute. Similarly, setting the seconds and minutes match bits causes an exact match of these values. Thus, an alarm occurs once per hour. Setting seconds, minutes, and hours causes a match once per day. Lastly, selecting all match values causes an exact time and date match. Selecting other bit combinations does not produce meaningful results; however, the alarm circuit must follow the functions described. There are two ways to detect an alarm event: by reading the AF flag or by monitoring the INT pin. The AF flag in the flags register at 0x1FFF0 indicates that a date or time match has occurred. The AF bit is set to `1' when a match occurs. Reading the flags or control register clears the alarm flag bit (and all others). A hardware interrupt pin is used to detect an alarm event.
Watchdog Timer
The watchdog timer is a free running down counter that uses the 32 Hz clock (31.25 ms) derived from the crystal oscillator. The oscillator must be running for the watchdog to function. It begins counting down from the value loaded in the watchdog timer register. The counter consists of a loadable register and a free running counter. On power up, the watchdog timeout value in register 0x1FFF7 is loaded into the counter load register. Counting begins on power up and restarts from the loadable value any time the Watchdog Strobe (WDS) bit is set to `1'. The counter is compared to the terminal value of 0. If the counter reaches this value, it causes an internal flag and an optional interrupt output. The timeout interrupt is prevented by setting WDS bit to `1' before the counter reaches `0'. This causes the counter to reload with the watchdog timeout value and get restarted. As long as the WDS bit is set before the counter reaches the terminal value, the interrupt and flag never occurs. New timeout values are written by setting the watchdog write bit to `0'. When the WDW is `0' (from the previous operation), new writes to the watchdog timeout value bits D5-D0 allow the modification of timeout values. When WDW is `1', then writes to bits D5-D0 are ignored. The WDW function allows to set the WDS bit without concern that the watchdog timer value is modified. A logical diagram of the watchdog timer is shown in Figure 3 on page 8. Note that setting the watchdog timeout value to `0' is otherwise meaningless and as a result, disables the watchdog function. The output of the watchdog timer is a flag bit WDF that is set if the watchdog is allowed to timeout. The flag is set upon a watchdog timeout and cleared when the flags control register is read by the user. The user can also enable an optional interrupt source to drive the INT pin if the watchdog timeout occurs.
Alarm
The alarm function compares user programmed values with the corresponding time of day values. When a match occurs, the alarm event occurs. The alarm drives an internal flag, AF, and may drive the INT pin if desired. There are four alarm match fields. They are date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to `0' indicates that the corresponding field is used in the match process.
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PRELIMINARY
CY14E104K/CY14E104M
Figure 3. Watchdog Timer Block Diagram
an interrupt output. Only one source is necessary to drive the pin. The user can identify the source by reading the flags or control register, which contains the flags associated with each source. All flags are cleared to `0' when the register is read. The cycle must be a complete read cycle (WE HIGH); otherwise, the flags are not cleared. The power monitor has two programmable settings that are explained in Power Monitor on page 8. After an interrupt source is active, the pin driver determines the behavior of the output. It has two programmable settings. Pin driver control bits are located in the interrupts register. According to the programming selections, the pin is driven in the backup mode for an alarm interrupt. In addition, the pin is an active LOW (open drain) or an active HIGH (push pull) driver. If programmed for operation during backup mode, it is active LOW. Lastly, the pin provides a one shot function so that the active condition is a pulse or a level condition. In one shot mode, the pulse width is internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller. In the level mode, the pin goes to its active polarity until the flags or control register is read by the user. This mode is used as an interrupt to a host microcontroller. The control bits are summarized as follows.
Power Monitor
The CY14E104K/CY14E104M provides a power management scheme with power fail interrupt capability. It also controls the internal switch to backup power for the clock and protects the memory from low VCC access. The power monitor is based on an internal band gap reference circuit that compares the VCC voltage to various thresholds. As described in the section AutoStore Operation on page 3, when VSWITCH is reached as VCC decays from power loss, a data store operation is initiated from SRAM to the nonvolatile elements, securing the last SRAM data state. Power is also switched from VCC to the backup supply (battery or capacitor) to operate the RTC oscillator. When operating from the backup source, no data is read or written and the clock functions are not available to the user. The clock continues to operate in the background. The updated clock data is available to the user after tHRECALL delay (see AutoStore/Power Up RECALL on page 16) after VCC is restored to the device.
Watchdog Interrupt Enable - WIE. When set to `1', the watchdog timer drives the INT pin and an internal flag when a watchdog timeout occurs. When WIE is set to `0', the watchdog timer affects only the internal flag. Alarm Interrupt Enable - AIE. When set to `1', the alarm match drives the INT pin and an internal flag. When set to `0', the alarm match only affects the internal flag. Power Fail Interrupt Enable - PFE. When set to `1', the power fail monitor drives the pin and an internal flag. When set to `0', the power fail monitor affects only the internal flag. High/Low - H/L. When set to a `1', the INT pin is active HIGH and the driver mode is push pull. The INT pin can drive HIGH only when VCC > VSWITCH. When set to `0', the INT pin is active LOW and the drive mode is open drain. Active LOW (open drain) is operational even in battery backup mode. Pulse/Level - P/L. When set to `1' and an interrupt occurs, the INT pin is driven for approximately 200 ms. When P/L is set to `0', the INT pin is driven HIGH or LOW (determined by H/L) until the flags or control register is read. When an enabled interrupt source activates the INT pin, an external host can read the flags or control register to determine the cause. All flags are cleared when the register is read. If the INT pin is programmed for level mode, then the condition clears and the INT pin returns to its inactive state. If the pin is programmed for pulse mode, then reading the flag also clears the flag and the pin. The pulse does not complete its specified duration if the flags or control register is read. If the INT pin is used as a host reset, then the flags or control register must not be read during a reset. During a power on reset with no battery, the interrupt register is automatically loaded with the value 24h. This enables the power fail interrupt with an active LOW pulse.
Interrupts
The CY14E104K/CY14E104M provides three potential interrupt sources. They include the watchdog timer, the power monitor, and the clock or calendar alarm. Each are individually enabled and assigned to drive the INT pin. In addition, each has an associated flag bit that the host processor can use to determine the cause of the interrupt. Some of the sources have additional control bits that determine functional behavior. In addition, the pin driver has three bits that specify its behavior when an interrupt occurs. The three interrupts each have a source and an enable. Both the source and the enable must be active (true HIGH) to generate
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PRELIMINARY
CY14E104K/CY14E104M
Figure 4. RTC Recommended Component Configuration
Recommended Values Y1 = 32.768KHz RF = 10M Ohm C1 = 0 C2 = 56 pF
.
Figure 5. Interrupt Block Diagram
Legend WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - HIGH/LOW
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PRELIMINARY
CY14E104K/CY14E104M
Table 3. RTC Register Map Register 0x1FFFF 0x1FFFE 0x1FFFD 0x1FFFC 0x1FFFB 0x1FFFA 0x1FFF9 0x1FFF8 OSCEN 0x1FFF7 0x1FFF6 0x1FFF5 0x1FFF4 0x1FFF3 0x1FFF2 0x1FFF1 0x1FFF0 WDF WDS WIE M M M M 0 WDW AIE 0 0 PFE 0 H/L 10s Alarm Date 10s Alarm Hours 10 Alarm Minutes 10 Alarm Seconds 10s Centuries AF PF OSCF 0 0 0 0 0 0 BCD Format Data D7 D6 0 0 0 0 D5 0 D4 10s Months 0 0 D3 D2 D1 Years Months Day Of Month Day of week Hours Minutes Seconds Calibration WDT P/L 0 0 Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Centuries CAL W R D0 10s Years Function/Range Years: 00-99 Months: 01-12 Day of Month: 01-31 Day of week: 01-07 Hours: 00-23 Minutes: 00-59 Seconds: 00-59 Calibration Values [7] Watchdog [7] Interrupts [7] Alarm, Day of Month: 01-31 Alarm, Hours: 00-23 Alarm, Minutes: 00-59 Alarm, Seconds: 00-59 Centuries: 00-99 Flags[7]
10s Day of Month 0 10s Minutes 10s Seconds Cal Sign 10s Hours
Note 7. This is a binary value, not a BCD value.
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PRELIMINARY
CY14E104K/CY14E104M
Table 4. Register Map Detail Time Keeping - Years D7 0x1FFFF D6 10s Years D5 D4 D3 D2 Years D1 D0
Contains the lower two BCD digits of the year. Lower nibble contains the value for years; upper nibble contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0-99. Time Keeping - Months D7 0x1FFFE 0 D6 0 D5 0 D4 10s Month D3 D2 Months D1 D0
Contains the BCD digits of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range for the register is 1-12. Time Keeping - Date D7 0x1FFFD 0 D6 0 D5 D4 D3 D2 D1 D0 10s Day of Month Day of Month
Contains the BCD digits for the date of the month. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 3. The range for the register is 1-31. Leap years are automatically adjusted for. Time Keeping - Day D7 0x1FFFC 0 D6 0 D5 0 D4 0 D3 0 D2 D1 Day of Week D0
Lower nibble contains a value that correlates to day of the week. Day of the week is a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day value, because the day is not integrated with the date. Time Keeping - Hours D7 0x1FFFB 12/24 D6 0 D5 10s Hours D4 D3 D2 Hours D1 D0
Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0-23. Time Keeping - Minutes D7 0x1FFFA 0 D6 D5 10s Minutes D4 D3 D2 Minutes D1 D0
Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0-59. Time Keeping - Seconds D7 0x1FFF9 0 D6 D5 10s Seconds D4 D3 D2 Seconds D1 D0
Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0-59. Calibration/Control 0X1FFF8 D7 OSCEN OSCEN D6 0 D5 Calibration Sign D4 D3 D2 Calibration D1 D0
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. On a no-battery power up, this bit is set to 0.
Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time-base. Sign Calibration These five bits control the calibration of the clock.
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PRELIMINARY
CY14E104K/CY14E104M
Table 4. Register Map Detail (continued) WatchDog Timer 0x1FFF7 WDS WDW D7 WDS D6 WDW D5 D4 D3 WDT D2 D1 D0
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is write only. Reading it always returns a 0. Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5-WDT0) so it cannot be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows bits 5-0 to be written on the next write to the watchdog register. The new value is loaded on the next internal watchdog clock after the write cycle is complete. This function is explained in more detail in Watchdog Timer on page 7. Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits are written only if the WDW bit was cleared to 0 on a previous cycle. Interrupt Status/Control D7 WIE D6 AIE D5 PFIE D4 0 D3 H/L D2 P/L D1 0 D0 0
WDT
0x1FFF6 WIE AIE PFIE H/L P/L
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF flag. Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the alarm match only affects the AF flag. Power Fail Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When set to 0, the power fail monitor affects only the PF flag. High/Low. When set to a 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open drain, active LOW. Pulse/Level. When set to a 1, the INT pin is driven active (determined by H/L) by an interrupt source for approximately 200 ms. When set to a 0, the INT pin is driven to an active level (as set by H/L) until the flags or control register is read. Alarm - Day D7 M D6 0 D5 D4 D3 D2 D1 Alarm Date D0
0x1FFF5
10s Alarm Date
Contains the alarm value for the date of the month and the mask bit to select or deselect the date value. M Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the date value. Alarm - Hours 0x1FFF4 D7 M D6 0 D5 D4 D3 D2 D1 Alarm Hours D0 10s Alarm Hours
Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the hours value. Alarm - Minutes 0x1FFF3 D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Minutes Alarm Minutes
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value. M Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the minutes value. Alarm - Seconds 0x1FFF2 D7 M D6 0 D5 D4 D3 D2 D1 D0 10s Alarm Seconds Alarm Seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds' value.
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PRELIMINARY
CY14E104K/CY14E104M
Table 4. Register Map Detail (continued) M Match. When this bit is set to 0, the seconds' value is used in the alarm match. Setting this bit to 1 causes the match circuit to ignore the seconds value. Time Keeping - Centuries 0x1FFF1 D7 0 0x1FFF0 WDF AF PF OSCF D7 WDF D6 0 D6 AF D5 D4 Flags D5 PF D4 OSCF D3 0 D2 CAL D1 W D0 R D3 D2 D1 Centuries D0 10s Centuries
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach 0 without being reset by the user. It is cleared to 0 when the Flags/Control register is read. Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the alarm registers with the match bits = 0. It is cleared when the Flags/Control register is read. Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold VSWITCH. It is cleared to 0 when the Flags/Control register is read. Oscillator Fail Flag. Set to 1 on power up only if the oscillator is not running in the first 5 ms of power on operation. This indicates that time counts are no longer valid. The user must reset this bit to 0 to clear this condition. The chip does not clear this flag. This bit survives power cycles. Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0, the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up. Write Time. Setting the W bit to 1 freeze updates of the timekeeping registers. The user can then write them with updated values. Setting the W bit to 0 transfers the contents of the time registers to the timekeeping counters. Read Time. Setting the R bit to 1 copies a static image of the timekeeping registers and places them in a holding register. The user can then read them without concerns over changing values causing system errors. The R bit going from 0 to 1 causes the timekeeping capture, so the bit must be returned to 0 before reading again.
CAL W R
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PRELIMINARY
CY14E104K/CY14E104M
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +150C Supply Voltage on VCC Relative to GND ..........-0.5V to 7.0V Voltage Applied to Outputs in High-Z State....................................... -0.5V to VCC + 0.5V Input Voltage.............................................-0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current[8] ..................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch Up Current ................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 4.5V to 5.5V 4.5V to 5.5V
DC Electrical Characteristics
Over the Operating Range (VCC = 4.5V to 5.5V) [10] Parameter Description ICC1 Average Vcc Current Test Conditions tRC = 15 ns Commercial tRC = 20 ns tRC = 25 ns tRC = 45 ns Dependent on output loading and cycle rate.Values Industrial obtained without output loads. IOUT = 0 mA Min Max 70 65 65 50 75 70 70 52 6 35 Unit mA mA mA mA mA mA mA mA
ICC2 ICC3[9]
ICC4
ISB
All Inputs Don't Care, VCC = Max. Average current for duration tSTORE Average VCC Current WE > (VCC - 0.2). All other I/P cycling. at tRC = 200 ns, 5V, Dependent on output loading and cycle rate. Values obtained 25C typical without output loads. Average VCAP Current All Inputs Don't Care, VCC = Max. during AutoStore Average current for duration tSTORE Cycle VCC Standby Current CE > (VCC - 0.2).All others VIN < 0.2V or >(VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0MHz. Input Leakage Current VCC = Max, VSS < VIN < VCC (except HSB) Input Leakage Current VCC = Max, VSS < VIN < VCC (for HSB) Off State Output VCC = Max., VIN = VSS < VIN < VCC, CE or OE > VIH Leakage Current Input HIGH Voltage Input LOW Voltage Output LOW Voltage Output HIGH Voltage Storage Capacitor -1 -100 -1
Average VCC Current during STORE
6
mA
3
mA
IIX
+1 +1 +1
A A A V V V V F
IOZ VIH VIL VOL VOH VCAP
IOUT = 4 mA IOUT = -2 mA Between VCAP pin and VSS, 5V Rated
2.2 VCC + 0.5 Vss - 0.5 0.8 0.4 2.4 61 82
Notes 8. Outputs shorted for no more than one second. Only one output is shorted at a time. 9. Typical conditions for the active current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 5V. Not 100% tested. 10. The HSB pin has IOUT=-10 uA for VOH of 2.4V.This parameter is characterized but not tested.
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PRELIMINARY
Capacitance
CIN COUT
CY14E104K/CY14E104M
In the following table, the capacitance parameters are listed. [11] Parameter Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max 7 7 Unit pF pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[11] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 44-TSOP II 31.11 5.56 54-TSOPII 30.73 6.08 Unit C/W C/W
JA JC
Figure 6. AC Test Loads
5.0V OUTPUT 30 pF
963 R1 R2 512
5.0V OUTPUT 5 pF
963 R1 R2 512
AC Test Conditions
Input Pulse Levels ................................................... 0V to 3V Input Rise and Fall Times (10% - 90%) ....................... <5 ns Input and Output Timing Reference Levels ....................1.5V Table 5. RTC Characteristics Parameters IBAK [12] VRTCbat [13] VRTCcap [14] tOCS Description RTC Backup Current RTC Battery Pin Voltage RTC Capacitor Pin Voltage RTC Oscillator Time to Start At Minimum Temperature from Power up or Enable At Minimum Temperature from Power up or Enable Test Conditions Commercial Industrial Commercial Industrial Commercial Industrial Commercial 1.8 1.8 1.5 1.5 Min Max 300 350 3.3 3.3 3.6 3.6 10 5 10 5 Units nA nA V V V V sec sec sec sec
At 25C Temperature from Power up or Enable Commercial Industrial
At 25C Temperature from Power up or Enable Industrial
Notes 11. These parameters are guaranteed but not tested. 12. From either VRTCcap or VRTCbat. 13. Typical = 3.0V during normal operation. 14. Typical = 2.4V during normal operation.
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PRELIMINARY
CY14E104K/CY14E104M
AC Switching Characteristics
Parameters Cypress Alt Parameters Parameters SRAM Read Cycle tACE tRC [15] tAA [16] tDOE tOHA tLZCE [17] tHZCE tHZOE
[17]
15 ns Description Min Max
20 ns Min Max
25 ns Min Max
45 ns Min Max Unit
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR
Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write 3 15 15 10 15 5 0 10 0 0 0 0 0 3 3 15
15 20 15 10 3 3 7 0 7 0 15 10 0 7 20 15 15 8 0 15 0 0 7 3 15
20 25 20 10 3 3 8 0 8 0 20 10 0 8 25 20 20 10 0 20 0 0 8 3 20
25 45 25 12 3 3 10 0 10 0 25 12 0 10 45 30 30 15 0 30 0 0 10 3 30
45 45 20
ns ns ns ns ns ns
15 15 45 20 15
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tLZOE [17]
[17]
tPU [11] tPD [11] tDBE tLZBE tHZBE tWC tPWE tSCE tSD tHD tAW tSA tHA
SRAM Write Cycle
tHZWE [17,18] tWZ tLZWE [17] tOW tBW -
15
ns ns ns
AutoStore/Power Up RECALL
Parameters tHRECALL [19] tSTORE [20] VSWITCH tVCCRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 CY14E104K/CY14E104M Min Max 20 15 4.4 Unit ms ms V s
Notes 15. WE must be HIGH during SRAM read cycles. 16. Device is continuously selected with CE and OE both LOW. 17. Measured 200 mV from steady state output voltage. 18. If WE is low when CE goes low, the outputs remain in the high impedance state. 19. tHRECALL starts from the time Vcc rises above VSWITCH. 20. If an SRAM write has not taken place since the last nonvolatile cycle, no STORE takes place.
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PRELIMINARY
CY14E104K/CY14E104M
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[21, 22] Parameters tRC tAS tCW tGHAX tRECALL tSS [23,24] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 15 ns Min 15 0 12 1 200 70 Max 20 0 15 1 200 70 15 ns Min Max Min 25 0 20 1 200 70 200 70 25 ns Max 45 ns Min 45 0 30 Max Unit ns ns ns ns s s
Hardware STORE Cycle
Parameters tDELAY [25] tHLHX Description Time Allowed to Complete SRAM Cycle Hardware STORE Pulse Width CY14E104K/CY14E104M Min 1 15 Max 70 Unit s ns
Switching Waveforms
Figure 7. SRAM Read Cycle #1: Address Controlled[15, 16, 26]
tRC
ADDRESS
t AA t OHA
DQ (DATA OUT) DATA VALID
Notes 21. The software sequence is clocked with CE controlled or OE controlled reads. 22. The six consecutive addresses must be read in the order listed in Table 1 on page 5. WE must be HIGH during all six consecutive cycles. 23. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 24. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See specific command. 25. On a hardware STORE initiation, SRAM operation continues to be enabled for time tDELAY to allow read and write cycles to complete. 26. HSB must remain HIGH during read and write cycles.
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PRELIMINARY
CY14E104K/CY14E104M
Switching Waveforms
(continued) Figure 8. SRAM Read Cycle #2: CE Controlled[15, 26, 28]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
tLZOE
BHE , BLE
tDOE
t HZOE
DQ (DATA OUT)
tLZBE t PU
tDBE
DATA VALID
tHZCE tHZBE
ACTIVE
ICC
STANDBY
Figure 9. SRAM Write Cycle #1: WE Controlled[18, 26, 27, 28]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE
BHE , BLE
tBW tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Notes 27. CE or WE must be > VIH during address transitions. 28. BHE and BLE are applicable for x16 configuration only.
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PRELIMINARY
CY14E104K/CY14E104M
Switching Waveforms
(continued) Figure 10. SRAM Write Cycle #2: CE Controlled[18, 26, 27, 28]
tWC
ADDRESS
tSA
CE
tSCE tAW tHA tPWE
WE
BHE , BLE
tBW
tSD tHD
DATA VALID
DATA IN
DATA OUT
HIGH IMPEDANCE
Figure 11. AutoStore/Power Up RECALL
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
Note 29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
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PRELIMINARY
CY14E104K/CY14E104M
Switching Waveforms
(continued) Figure 12. CE Controlled Software STORE/RECALL Cycle[22]
Figure 13. OE Controlled Software STORE/RECALL Cycle[22]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tAS
OE
tCW tGHAX
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
DQ (DATA)
DATA VALID
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PRELIMINARY
CY14E104K/CY14E104M
Switching Waveforms
(continued) Figure 14. Hardware STORE Cycle[25]
Figure 15. Soft Sequence Processing[23, 24]
tSS
tSS
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PRELIMINARY
CY14E104K/CY14E104M
PART NUMBERING NOMENCLATURE CY 14 E 104 K - ZS P 15 X C T
Option: T - Tape & Reel Blank - Std.
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
Pb-Free
Speed: 15 - 15 ns 20 - 20 ns 25 - 25 ns 45 - 45 ns
P - 54 Pin Blank - 44 Pin
Package:
ZS - TSOP II Data Bus: K - x8 + RTC M - x16 + RTC Voltage: E - 5.0V NVSRAM 14 - AutoStore + Software Store + Hardware Store
Density: 104 - 4 Mb
Cypress
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PRELIMINARY
CY14E104K/CY14E104M
Ordering Information
Speed (ns) 15 Ordering Code CY14E104K-ZS15XCT CY14E104K-ZS15XIT CY14E104K-ZS15XI CY14E104M-ZS15XCT CY14E104M-ZS15XIT CY14E104M-ZS15XI CY14E104K-ZSP15XCT CY14E104K-ZSP15XIT CY14E104K-ZSP15XI CY14E104M-ZSP15XCT CY14E104M-ZSP15XIT CY14E104M-ZSP15XI 20 CY14E104K-ZS20XCT CY14E104K-ZS20XIT CY14E104K-ZS20XI CY14E104M-ZS20XCT CY14E104M-ZS20XIT CY14E104M-ZS20XI CY14E104K-ZSP20XCT CY14E104K-ZSP20XIT CY14E104K-ZSP20XI CY14E104M-ZSP20XCT CY14E104M-ZSP20XIT CY14E104M-ZSP20XI 25 CY14E104K-ZS25XCT CY14E104K-ZS25XIT CY14E104K-ZS25XI CY14E104M-ZS25XCT CY14E104M-ZS25XIT CY14E104M-ZS25XI CY14E104K-ZSP25XCT CY14E104K-ZSP25XIT CY14E104K-ZSP25XI CY14E104M-ZSP25XCT CY14E104M-ZSP25XIT CY14E104M-ZSP25XI Package Diagram 51-85087 51-85087 51-85087 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85160 51-85160 51-85160 Package Type 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
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PRELIMINARY
CY14E104K/CY14E104M
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14E104K-ZS45XCT CY14E104K-ZS45XIT CY14E104K-ZS45XI CY14E104M-ZS45XCT CY14E104M-ZS45XIT CY14E104M-ZS45XI CY14E104K-ZSP45XCT CY14E104K-ZSP45XIT CY14E104K-ZSP45XI CY14E104M-ZSP45XCT CY14E104M-ZSP45XIT CY14E104M-ZSP45XI Package Diagram 51-85087 51-85087 51-85087 51-85087 51-85087 51-85087 51-85160 51-85160 51-85160 51-85160 51-85160 51-85160 Package Type 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 44-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII 54-pin TSOPII Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
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PRELIMINARY
CY14E104K/CY14E104M
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
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PRELIMINARY
CY14E104K/CY14E104M
Package Diagrams
(continued) Figure 17. 54-Pin TSOP II (51-85160)
51-85160-**
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PRELIMINARY
CY14E104K/CY14E104M
Document History Page
Document Title: CY14E104K/CY14E104M 4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock Document Number: 001-09604 Orig. of Rev. ECN No. Submission Change Description of Change Date ** 493192 See ECN TUP New Data Sheet *A 499597 See ECN PCI Removed 35 ns speed bin. Added 55 ns speed bin. Updated AC table for the same. Changed "Unlimited" read/write to "infinite" read/write Features section: Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles. Shaded Commercial grade in operating range table. Modified Icc/Isb specs. Changed VCAP value in DC table Modified part nomenclature table. Changes reflected in the ordering information table. *B 517928 See ECN TUP Removed 55ns speed bin Changed the pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA. Changed ICC4 to 3mA Changed tSTORE to 15ns. Changed tPWE to 10ns Changed tSCE to 15ns. Changed tSD to 5ns Changed tAW to 10ns. Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min. specification for Vswitch Changed tGLAX to 1ns. Added tDELAY max. of 70us Changed tSS specification from 70us min. to 70us max. *C 774157 See ECN UHA Changed the data sheet from Advance information to Preliminary Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW to15ns in 15ns part Changed Note 1 to include 16Mbit In AC test loads changed the value of R1 to 963 and R2 to 512 *D 914280 See ECN UHA Changed the figure-14 title from 54-Pb to 54 Pin Included all the information for 45ns part in this data sheet *E 1890926 See ECN vsutmp8 Updated logic block diagram /AESA Added Footnote 1, 2 and 3. Updated Pin definition table Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8). Corrected typo in VIL min spec Changed Vswitch value from 2.65V to 4.4V Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA updated ordering information table Changed package diagrams title The pins X1 and X2 interchanged in 44TSOP II(x8) and 54TSOP II(x16) pinout. *F 2267286 See ECN GVCH/ Rearranging of "Features". Updated Figure 2 (Autostore mode) PYRS RTC Register Map:Register 0x1FFF6:Changed D4 from ABE to 0 Register Map Detail:0x1FFF6:Changed D4 from ABE to 0 and removed ABE Info Changed ICC2 & ICC4 from 3mA to 6mA. Changed ICC3 from 13mA to 15mA Changed ISB from 2mA to 3mA Added input leakage current (IIX) for HSB in DC Electrical Characteristics table Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Changed Vrtccap max from 2.7V to 3.6V. Changed tRECALL from 100 to 200us 45ns speed information is added in Software Controlled Store/Recall Cycle Table Corrected typo in tAW value from 15ns to 10ns for 15ns part Reframed footnote 6, 18 and 25. Added footnote 29 Added footnote 18 to figure 8 and footnote 18, 26 and 27 to figure 9. Document #: 001-09604 Rev. *H Page 27 of 28
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PRELIMINARY
CY14E104K/CY14E104M
Document Title: CY14E104K/CY14E104M 4 Mbit (512K x 8 / 256K x 16) nvSRAM with Real-Time-Clock Document Number: 001-09604 Orig. of Rev. ECN No. Submission Change Description of Change Date *G 2483627 See ECN GVCH/ Removed 8 mA typical ICC at 200 ns cycle time in Feature section PYRS Referenced footnote 9 to ICC3 in DC Characteristics table Changed ICC3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRC. Changed VRTCcap minimum value from 1.2V to 1.5V Figure 12:Changed tSA to tAS and tSCE to tCW *H 2519319 06/20/08 GVCH/ Added 20 ns access speed in "Features" PYRS Added ICC1 for tRC=20 ns for both industrial and Commecial temperature Grade Updated thermal resistance values for 44-TSOP II and 54-TSOP II packages Added AC Switching Characteristics specs for 20 ns access speed Added Software controlled STORE/RECALL cycle specs for 20 ns access speed Updated ordering information and Part numbering nomenclature
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(c) Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-09604 Rev. *H
Revised June 20, 2008
Page 28 of 28
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